1. The Field of the Invention
The present invention relates to methods for forming silicon structures. More particularly, the present invention relates to methods for forming a silicon structure of increased surface area by forming roughened surfaces on opposite sides of the silicon structure. The present invention is also directed to a capacitor having capacitor plates that similarly have an increased surface area on opposite sides thereof
2. The Relevant Technology
Integrated circuits are found on microchips and provide the logic and memory of computers and other such intelligent electronic devices. These integrated circuits are now being formed with an improved efficiency that has made computers and other intelligent electronic devices more affordable. Continual progress in integrated circuit manufacturing processes has also led to an increasingly smaller scale and a greater functionality of intelligent electronic devices.
Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term "substrate" refers to any supporting structure including but not limited to the semiconductor substrates described above. The conventional semiconductor devices which are formed on the semiconductor wafer include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor wafer.
The computer and electronics industry is constantly under market demand to increase the speed at which integrated circuits operate, to increase the capabilities of integrated circuits, and to reduce the cost of integrated circuits. One manner of accomplishing this task is to increase the density with which the semiconductor devices can be formed on a given surface area of a single semiconductor wafer. In so doing, the semiconductor devices must be decreased in dimension in a process known as miniaturization. In order to meet market demands and further the miniaturization of integrated circuits, the processes by which the semiconductor devices are formed are in need of improvement.
The capacitor is a structure which is frequently formed in integrated circuit manufacturing and for which an improved method of formation is needed. The capacitor is formed with a storage node, a cell plate, and an intervening dielectric layer. The storage node and the cell plate are typically patterned out of polysilicon by conventional photolithography and dry etching. The dielectric layer is formed in an intervening process between the formation of the storage node and the cell plate, typically by chemical vapor deposition (CVD) of silicon nitride through exposure of the polysilicon of the storage node to oxygen at an elevated temperature.
An important consideration in forming capacitors in integrated circuits is surface area. A large surface area of the storage node and cell plate is necessary in order to provide high capacitance and therefore optimal performance of the capacitor. Balanced against this need is the competing requirement that the capacitor also occupy a minimum of space on the silicon substrate of a semiconductor wafer on which the capacitor is formed. One manner in which the semiconductor industry has approached minimal space capacitor formation is to form the capacitor at a significant distance above the silicon substrate. When so doing, one of the storage node and the cell plate are typically wrapped around the other, forming what is known as a stacked capacitor.
While the use of stacked capacitors has effectively increased capacitor surface area, one further problem common with the various configurations of stacked capacitors and the processes used to form them is that the processes are generally complicated and lengthy, thereby increasing the opportunities for defect conditions to occur and driving up integrated circuit manufacturing cost. Generally, the greater the surface area provided by the process, the more elaborate and expensive the process is. Thus, even stacked capacitors are reaching the limits of usable surface area that can be provided in a cost effective manner.
Consequently, an improved method is needed which forms a capacitor of a large surface area and which forms the capacitor in a manner that occupies a minimum of space on the silicon substrate. In addition, such a method is needed which can be conducted in a simple and cost effective manner.